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HT1620
RAM Mapping 324 LCD Controller for I/O mC
Features
* * * * * * * * *
Logic operating voltage: 2.4V~3.3V LCD voltage: 3.6V~4.9V Low operating current <3mA at 3V External 32.768kHz crystal oscillator Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty LCD applications Internal time base frequency sources Two selectable buzzer frequencies (2kHz/4kHz) Built-in capacitor type bias charge pump Time base or WDT overflow output
* * * * * * * * *
8 kinds of time base/WDT clock source 324 LCD driver Built-in 324-bit display RAM 3-wire serial interface Internal LCD driving frequency source Software configuration feature R/W address auto increment Data mode and command mode instructions Three data accessing modes
General Description
The HT1620 is a 128 pattern (324), memory mapping, and multi-function LCD driver. The S/W configuration feature of the HT1620 makes it suitable for multiple LCD applications including LCD modules and display subsystems. Only three or four lines are required for the interface between the host controller and the HT1620. The HT1620 consumes low operating current owing to adopting capacitor type bias charge pump. The HT162X series have many kinds of products that match various applications.
Selection Table
HT162X COM SEG Built-in Osc. Crystal Osc. O
HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
4 32
4 32 O O
8 32 O
8 32 O
8 48 O O
8 64 O O
16 48 O O
16 64 O
16 64 O
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Block Diagram
OSCO OSCI CS RD WR DATA VDD VSS Con an T im C ir c tro l d in g u it
D is p la y R A M
COM0 L C D D r iv e r / B ia s C ir c u it COM3 SEG0 SEG 31 CC1 CC2 VO 15N VEE
BZ BZ
T o n e F re q u e n c y G e n e ra to r
W a tc h d o g T im e r & T im e B a s e G e n e r a to r
IR Q
Notes: CS: Chip selection BZ, BZ: Tone outputs WR, RD, DATA: Serial interface COM0~COM3, SEG0~SEG31: LCD outputs IRQ: Time base or WDT overflow output VO15N: Half voltage circuit output pin VEE: Double voltage circuit output pin CC1/CC2: External capacitor pin, for double voltage and half voltage circuit use
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Pin Assignment
CS RD WR DATA VSS OSCO OSCI VDD IR Q BZ BZ CC1 NC
64 63 62 61 60 59 58 57 56 55 54 53 52 1 51 2 50 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 49 48 47 46 45 44
NC C
VO1 V CO CO CO CO SE SE SE SE SE SE SE SE SE
NC C2 5N EE M0 M1 M2 M3 G0 G1 G2 G3 G4 G5 G6 G7 G8 NC
NC NC NC NC NC SE SE SE SE SE SE SE SE SE SE SE SE NC NC G 31 G 30 G 29 G 28 G 27 G 26 G 25 G 24 G 23 G 22 G 21 G 20
HT1620 64 Q FP
43 42 41 40 39 38 37 36 35 34 33
SE SE SE SE SE SE SE SE SE SE SE NC G9 G 19 G 18 G 17 G 16 G 15 G 14 G 13 G 12 G 11 G 10
NC
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Pad Assignment
OSCO DATA OSCI VDD VSS CC1 51 1 2 3 4 5 6 7 8 9 10 11 12 13 (0 ,0 ) 39 38 37 36 35 34 33 32 31 30 29 14 SEG6 15 SEG7 16 SEG8 17 SEG9 18 SEG 10 19 SEG 11 20 SEG 12 21 SEG 13 22 SEG 14 23 SEG 15 24 SEG 16 25 SEG 17 26 SEG 18 27 SEG 19 28 SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 IR Q WR RD CS BZ 50 BZ 49
CC2 VO 15N VEE COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5
48
47
46
45
44
43
42
41
40
Chip size: 142 141 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
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HT1620
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 X -61.58 -61.83 -61.83 -61.83 -61.83 -61.83 -61.83 -61.83 -61.83 -61.83 -61.83 -61.83 -61.83 -60.90 -54.27 -47.64 -41.01 -34.38 -27.75 -21.12 -14.49 -7.86 -1.23 5.40 12.03 18.66 Y 63.62 50.83 43.73 37.10 30.47 23.84 17.21 10.58 3.95 -2.68 -9.31 -15.94 -22.57 -64.26 -64.26 -64.26 -64.26 -64.26 -64.26 -64.26 -64.26 -64.26 -64.26 -64.26 -64.26 -64.26 Pad No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 X 25.29 66.98 66.98 66.98 66.98 66.98 66.98 66.98 66.98 66.98 66.98 66.98 66.98 65.71 59.08 52.45 40.59 29.75 22.95 16.32 9.56 -2.21 -21.80 -39.52 -49.60 Unit: mil Y -64.26 -62.65 -56.01 -49.38 -42.76 -36.13 -29.50 -22.86 -16.24 -9.60 -2.97 3.65 10.28 64.39 64.39 64.39 64.39 64.39 64.39 64.39 64.39 64.30 64.39 64.39 63.62
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Pad Description
Pad No. 2 3 4~7 8~39 Pad Name VO15N VEE COM0~COM3 SEG0~SEG31 I/O O 3/4 O O Description Half voltage circuit output pin Double voltage circuit output pin LCD common outputs LCD segment outputs Chip selection input with pull-high resistor When the CS is logic high, the data and command, read from or written to the HT1620 are disabled. The serial interface circuit is also reset. But if the CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1620 are all enabled. READ clock input with pull-high resistor Data in the RAM of the HT1620 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the DATA line. The host controller can use the next raising edge to latch the clocked out data. WRITE clock input with pull-high resistor Data on the DATA line are latched into the HT1620 on the rising edge of the WR signal. Serial data input/output with pull-high resistor Negative power supply, Ground The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. Positive power supply Time base or WDT overflow flag, NMOS open drain output 2kHz or 4kHz tone frequency output pair (tri-state output buffer) External capacitor pin, for double voltage and half voltage circuit use
40
CS
I
41
RD
I
42 43 44 45 46 47 48 49, 50 51, 1
WR DATA VSS OSCO OSCI VDD IRQ BZ, BZ CC1, CC2
I I/O 3/4 O I 3/4 O O I
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 3.6V Input Voltage .................VSS-0.3V to VDD+0.3V Storage Temperature.................-50 C to 125 C Operating Temperature...............-25 C to 75 C
o o o o
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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D.C. Characteristics
Symbol VDD IDD ISTB VIL VIH IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 RPH Parameter Operating Voltage Operating Current Standby Current Input Low Voltage Input High Voltage DATA, BZ, BZ, IRQ DATA, BZ, BZ LCD Common Sink Current LCD Common Source Current LCD Segment Sink Current LCD Segment Source Current Pull-high Resister Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V No load* No load* DATA, WR, CS, RD DATA, WR, CS, RD VOL=0.3V VOH=2.7V VOL=0.3V VOH=2.7V VOL=0.3V VOH=2.7V DATA, WR, CS, RD Conditions 3/4 Min. 2.4 3/4 3/4 3/4 2.4 0.8 -0.6 80 -70 70 -30 40 Typ. 3/4 2 3/4 3/4 3/4 1.6 -1.2 150 -120 140 -60 80 Max. 3.3 3 1 0.6 3.0 3/4 3/4 3/4 3/4 3/4 3/4 150 Ta=25C Unit V mA mA V V mA mA mA mA mA mA kW
* No load: LCD OFF, Buzzer OFF, CS=WR=RD=High
A.C. Characteristics
Symbol fSYS Parameter System Clock LCD Frame Frequency fLCD LCD Frame Frequency 1/2 Duty LCD Frame Frequency 1/3 Duty LCD Frame Frequency 1/4 Duty tCOM fCLK fTONE LCD Common Period Serial Data Clock Tone Frequency Test Conditions VDD 3V 3/4 3/4 3/4 3/4 3/4 3V 3/4 n: Number of COM Write mode Read mode 3/4 Crystal 32kHz Conditions Crystal 32kHz Min. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Ta=25C Typ. Max. Unit 32 64 64 56 64 n/fLCD 3/4 3/4 2 or 4 3/4 3/4 3/4 3/4 3/4 3/4 150 75 3/4 kHz Hz Hz Hz Hz s kHz kHz kHz
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Symbol tCS tCLK tr, tf tsu th tsu1 th1 Parameter Serial Interface Reset Pulse Width (Figure 3) WR, RD Input Pulse Width (Figure 1) Rise/Fall Time Serial Data Clock Width (Figure 1) Setup Time for DATA to WR, RD Clock Width (Figure 2) Hold Time for DATA to WR, RD Clock Width (Figure 2) Setup Time for CS to WR,RD Clock Width (Figure 3) Hold Time for CS to WR, RD Clock Width (Figure 3) Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V CS Write mode Read mode 3/4 3/4 3/4 3/4 3/4 Conditions Min. 3/4 3.34 6.67 3/4 3/4 3/4 3/4 3/4 Typ. Max. Unit 250 3/4 3/4 120 120 120 100 100 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 ns ms ns ns ns ns ns
V A L ID D A T A DB V th
u
DD
tf W R,RD C lo c k 90% 50% 10%
tr V tC
LK
50% ts
GND V
DD
DD
tC
GND
LK
W R,RD C lo c k
50%
GND
Figure 1
Figure 2
tC
S
CS
50% ts
u1
V
DD
th
1
GND
V
DD
W R,RD C lo c k
50% F IR S T C lo c k
LAST C lo c k
GND
Figure 3
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Functional Description
Display memory - RAM structure The static display RAM is organized into 324 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MOD IFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns.
COM3 SEG0 SEG1 SEG2 SEG3 3 2 A d d r e s s 6 b its (A 5 , A 4 , ..., A 0 ) 1 COM2 COM1 COM0 0
Buzzer tone output A simple tone generator is implemented in the HT1620. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. LCD driver The HT1620 is a 128 (324) pattern LCD driver. It can be configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of LCD driver by the S/W configuration. This feature makes the HT1620 suitable for multiple LCD applications. The LCD driving clock is derived from the system clock. The value of the driving clock is always 256Hz even when it is at a 32.768kHz crystal oscillator frequency. The LCD corresponding commands are summarized in the table. The bold form of 1 0 0, namely 1 0 0, indicates the command mode ID. If successive commands have been issued, the command mode ID will be omitted, except for the first command. The LCD OFF command turns the LCD display off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns the LCD display on by enabling the LCD bias generator. The BIAS and COM are the LCD panel related commands. With the use of the LCD related commands, the HT1620 can be compatible with most types of LCD panels.
SEG 31 D 3 D 2 D 1 D 0
31 Addr D a ta
D a ta 4 b its (D 3 , D 2 , D 1 , D 0 )
RAM mapping Time base and watchdog timer - WDT The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will stay at a logic low level until the CLR WDT or the IRQ DIS command is issued.
T im e B a s e C lo c k S o u r c e /2 5 6 VDD CLR T im e r W DT /4 D CK R
T IM E R
E N /D IS
IR Q
W D T E N /D IS Q IR Q E N /D IS
CLR
W DT
Timer and WDT configurations
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HT1620
Name LCD OFF LCD ON Command Code 10000000010X 10000000011X Function Turn off LCD outputs Turn on LCD outputs c=0: 1/2 bias option c=1: 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option Interfacing Only four lines are required to interface with the HT1620. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1620. If the CS pin is set to 1, the data and command issued between the host controller and the HT1620 are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the HT1620. The DATA line is the serial data input/output line. Data to be read or written or commands to be written have to be passed through the DATA line. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DATA line. It is recommended that the host controller read in correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DATA line are all clocked into the HT1620 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1620. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by connecting with the IRQ pin of the HT1620.
BIAS and COM
1000010abXcX
Command format The HT1620 can be configured by the S/W setting. There are two mode commands to configure the HT1620 resources and to transfer the LCD display data. The configuration mode of the HT1620 is called command mode, and its command mode ID is 1 0 0. The command mode consists of a system configuration command, a system frequency selection command, an LCD configuration command, a tone frequency selection command, a timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following are the data mode IDs and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Mode Data Data Data ID 110 101 101
Command 1 0 0
The mode command should be issued before the data or command is transferred. If successive commands have been issued, the command mode ID, 1 0 0, can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will be reset also. Once the CS pin returns to 0, a new operation mode ID should be issued first.
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Timing Diagrams
READ mode (command code: 1 1 0)
CS
WR
RD 1 1 0 A5 A4 A3 A2 A1 A0 M e m o ry A d d re s s 1 (M A 1 ) D0 D1 D2 D3 D a ta (M A 1 ) 1 1 0 A5 A4 A3 A2 A1 A0 M e m o ry A d d re s s 2 (M A 2 ) D0 D1 D2 D3 D a ta (M A 2 )
DATA
READ mode (successive address reading)
CS
WR
RD 1 1 0 A5 A4 A3 A2 A1 A0 M e m o ry A d d re s s (M A ) D0 D1 D2 D3 D a ta (M A ) D0 D1 D2 D3 D a ta (M A + 1 ) D0 D1 D2 D3 D a ta (M A + 2 ) D0 D1 D2 D3 D a ta (M A + 3 ) D0
DATA
WRITE mode (command code: 1 0 1)
CS
WR 1 0 1 A5 A4 A3 A2 A1 A0 M e m o ry A d d re s s 1 (M A 1 ) D0 D1 D2 D3 D a ta (M A 1 ) 1 0 1 A5 A4 A3 A2 A1 A0 M e m o ry A d d re s s 2 (M A 2 ) D0 D1 D2 D3 D a ta (M A 2 )
DATA
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WRITE mode (successive address writing)
CS
WR 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0 M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )
DATA
Note: It is recommended that the host controller should read with the data from the DATA line between the raising edge of the RD line and the falling edge of the next RD line. READ-MODIFY-WRITE mode (command code: 1 0 1)
CS
WR
RD 1 0 A5 A4 A3 A2 A1 A0 M e m o ry A d d re s s 1 (M A 1 ) D0 D1 D2 D3 D a ta (M A 1 ) D0 D1 D2 D3 D a ta (M A 1 ) 1 0 A5 A4 A3 A2 A1 A0 M e m o ry A d d re s s 2 (M A 2 ) 1 D0 D1 D2 D3 D a ta (M A 2 )
DATA
1
READ-MODIFY-WRITE mode (successive address accessing)
CS
WR
RD 1 0 1 A5 A4 A3 A2 A1 A0 M e m o ry A d d re s s (M A ) D0 D1 D2 D3 D a ta (M A ) D0 D1 D2 D3 D a ta (M A ) D0 D1 D2 D3 D a ta (M A + 1 ) D0 D1 D2 D3 D a ta (M A + 1 ) D0 D1 D2 D3 D a ta (M A + 2 ) D0
DATA
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Command mode (command code: 1 0 0)
CS
WR 1 0 0 C8 C7 C6 C5 C4 C3 C2 C1 C om m and 1 C0 C8 C o m m a n d ... C7 C6 C5 C4 C3 C2 C1 C om m and i C0 C om m and or D a ta M o d e
DATA
Mode (data and command mode)
CS
WR
DATA
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
RD
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Application Circuits
VDD 0 .1 m F 0 .1 m F 3M W VDD 0 .1 m F
CC1 * CS RD WR DATA * R IR Q
CC2
VO 15N
VEE OSCI C ry s ta l 32768H z O s c illa to r
mC
HT1620
OSCO BZ
P ie z o COM0~COM3 SEG 0~SEG 31 BZ
1 /2 o r 1 /3 B ia s ; 1 /2 , 1 /3 o r 1 /4 D u ty
LC D Panel
* Notes: The connection of the IRQ and RD pin is selectable depending on the requirement of the mC. VDD=2.4V~3.3V, VEE=-1/2 VDD, VLCD (LCD voltage)=VDD-VEE=3/2 VDD=3.6V~4.9V. Adjust R (external pull-high resistance) to fit users time base clock.
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Command Summary
Name READ WRITE READ MODIFY WRITE SYS DIS SYS EN LCD OFF LCD ON ID Command Code D/C D D D C C C C C C C C C C C Function Read data from the RAM Write data to the RAM Read and write to the RAM Turn off both system oscillator and LCD bias generator Turn on system oscillator Turn off LCD bias generator Turn on LCD bias generator Disable time base output Disable WDT time-out flag output Enable time base output Enable WDT time-out flag output Turn off tone outputs Clear the contents of the time base generator Clear the contents of the WDT stage LCD 1/2 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option LCD 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option Tone frequency, 4kHz Tone frequency, 2kHz Disable IRQ output Enable IRQ output Yes Yes Yes Yes Yes Yes Def. 1 1 0 A5A4A3A2A1A0D0D1D2D3 1 0 1 A5A4A3A2A1A0D0D1D2D3 1 0 1 A5A4A3A2A1A0D0D D2D3 1 0 0 0000-0000-X 1 0 0 0000-0001-X 1 0 0 0000-0001-X 1 0 0 0000-0011-X
TIMER DIS 1 0 0 0000-0100-X WDT DIS TIMER EN WDT EN TONE OFF 1 0 0 0000-0101-X 1 0 0 0000-0010-X 1 0 0 0000-0111-X 1 0 0 0000-1000-X
CLR TIMER 1 0 0 0000-1101-X CLR WDT 1 0 0 0000-111X-X
BIAS 1/2
1 0 0 0010-abX0-X
C
BIAS 1/3 TONE 4K TONE 2K IRQ DIS IRQ EN
1 0 0 0010-abX1-X 1 0 0 010X-XXXX-X 1 0 0 0110-XXXX-X 1 0 0 100X-0XXX-X 1 0 0 100X-1XXX-X
C C C C C
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Name F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL
,
ID
Command Code
D/C C C C C C C C C C C
Function Time base clock output: 1Hz The WDT time-out flag after: 4s Time base clock output: 2Hz The WDT time-out flag after: 2s Time base clock output: 4Hz The WDT time-out flag after: 1s Time base clock output: 8Hz The WDT time-out flag after: 1/2 s Time base clock output: 16Hz The WDT time-out flag after: 1/4 s Time base clock output: 32Hz The WDT time-out flag after: 1/8 s Time base clock output: 64Hz The WDT time-out flag after: 1/16 s Time base clock output: 128Hz The WDT time-out flag after:1/32 s Test mode, user dont use. Normal mode
Def.
1 0 0 101X-0000-X 1 0 0 101X-0001-X 1 0 0 101X-0010-X 1 0 0 101X-0011-X 1 0 0 101X-0100-X 1 0 0 101X-0101-X 1 0 0 101X-0110-X 1 0 0 101X-0111-X 1 0 0 1110-0000-X 1 0 0 1110-0011-X
Yes
Yes
Notes: X : Don t care A5~A0 : RAM addresses D3~D0 : RAM data D/C : Data/command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from a 32.768kHz crystal oscillator. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1620 after power on reset, for power on reset may fail, which in turn leads to malfunctioning of the HT1620.
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Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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